Memory devices are in widespread use in computers, particularly personal computers. The system memory of such computers is generally provided by dynamic random access memories ("DRAMs"). DRAMs were initially asynchronous in which commands and addresses were received and processed by DRAMs at a rate that was not determined by a periodic signal. However, in an attempt to reduce memory access times and facilitate pipelining of memory accesses, synchronous DRAMs ("SDRAMs") were developed.
In a SDRAM, memory accesses are synchronized to an external clock that is applied to the DRAM so that one memory access, i.e., a read or write, occurs each period of the clock. An example of a conventional SDRAM 40 is shown in FIG. 1. The SDRAM 40 has as its central memory element a memory array 42 that is segmented into two banks 44, 46. The SDRAM 40 operates under control of a logic controller 48 that receives a system clock signal CLK, a clock-enable signal CKE, and several command signals that control reading from and writing to the SDRAM 40. Among the command signals are a chip-select signal CS*, a write-enable signal WE*, a column address strobe signal CAS*, and a row address strobe signal RAS*. (The asterisk next to the command signals CS, WE, CAS, and RAS indicate that these signals are active low signals, i.e., the command signals CS*, WE*, CAS*, and RAS* go to a low logic level when active).
In addition to the command signals, the SDRAM 40 also receives addresses from an address bus 52, and receives or outputs data on a data bus 60. The received addresses are either bank/row addresses or column addresses. An address on the address bus 52 is designated as a row addresses by a row address strobe RAS* signal transitioning active low when the address is present on the address bus. An address on the address bus 52 is designated as a column addresses by a column address strobe CAS* signal transitioning active low when the address is present on the address bus. As explained below, column addresses can also be generated internally. In any case, addresses from the address bus 52 are clocked into the SDRAM 40 through an address register or address latch 62. If an address is a row address, the address is coupled to the array 42 through a row address path 64. The row address path 64 includes a row address multiplexer 66 that receives the external row address from the address latch 62 and receives an internal row address from a refresh circuit 67. The row address multiplexer 66 provides the row addresses to either of two row address latches 70 depending upon the logic state of the bank address BA. The row address latches 70 latch the row addresses and provide the row addresses to respective row decoders 72. The row decoders 72 take the 11-bit address from the row address latch 70 and activate a selected one of 2,048 row address lines 73. The row address lines 73 are conventional lines for selecting row addresses of locations in the memory array 42. As noted above, the following discussion assumes that the row address has been selected and that the selected row is activated.
After a row address has been received and latched by RAS* going low, a column address may be latched responsive to a column address strobe signal CAS* going active low. If the address received at the address latch 62 is a column address, it is transmitted to the 1/0 interface 54 and the memory array 42 through a column address path 76. The column address path includes a column address counter/latch 78 that receives an initial column address from the address latch or buffer 62 and thereafter increments the address once each cycle of the CLK signal. The column address from the column address counter/latch 78 is thus an internally generated column address, as mentioned above.
The internal column address from the column address counter/latch 78 and an external column address from the address latch or buffer 62 are each applied to a multiplexer 79. The multiplexer 79 selects one of these column addresses based on the nature of the current memory access. If the current memory access is one of several identical memory accesses (i.e., a READ or a WRITE) to successive columns of a row, known as a "burst" memory access, the multiplexer 79 selects the internal address from the column address counter/latch 78 unless a new command is received. If, during a burst memory access, e.g., a burst READ, a new command, e.g., a burst WRITE, is received, the multiplexer 79 selects an external column address from the address latch or buffer 62.
In operation, the SDRAM 40 assumes a number of states before and during a memory transfer. Initially, the SDRAM 40 is in an idle state prior to the start of a memory transfer. When data are to be read from or written to the memory device, a row address is applied to the address bus 52 and an active low RAS* signal is applied to the command decoder in the logic controller 48. Thus, in the idle state, the only address used by the SDRAM 40 is an external row address. There is therefore never any need to use an internal address in the idle state. The transition of the RAS* signal to an active low state transitions the SDRAM 40 from the idle state to the row active state.
During the row active state, the memory cells in a selected row of the array 42 that corresponds to the row address are coupled to respective digit lines. As is well understood in the art, there are a set of complementary digit lines for each column of the memory arrays 42. Once the SDRAM 40 has transitioned to the row active state, the SDRAM 40 can transition to the column command state responsive to the RAS* signal transitioning high and the CAS* signal transitioning active low. In the column command state, the SDRAM 40 can receive and process a column address and a column command, such as a READ or a WRITE command. Thus, once the SDRAM 40 transitions from the row active state to the column command state, the SDRAM 40 can process a column address that, as explained above, can be either an external column address applied to the address bus 52 or an internal column address generated by the column address counter latch. When a memory command is received that is not for a burst memory access, the multiplexer 79 selects an external column address from the address latch or buffer 62. In a burst memory transfer, the column address counter/latch 78 increments the initial column address once each cycle of the CLK signal to generate a number of sequential column addresses corresponding to the length of the burst.
After data are read from or written to the SDRAM 40, the RAS* signal transitions inactive high to transition the SDRAM 40 back to the idle state during which precharging of the array 42 occurs before the start of another memory access.
As explained further below, the time required to determine whether an internal column address or an external column address should be selected by the multiplexer 79 can significantly slow the rate at which memory accesses can occur. The inventive method and apparatus is adapted to allow this determination to be made at an earlier time so that memory accesses can occur at a faster rate.
After the multiplexer has selected either an internal address or an external address, the multiplexer 79 couples the selected column address to a pre-decoder 102 and a latch 82. The pre-decoder 102 partially decodes the column address and passes it to a column decoder 84 to complete the decoding. The decoder 84 then selects the column to which data are to be read from or written to.
The input data path 56 transmits data from the data bus 60 to the I/O interface 54. The output data path 58 transmits data from the I/O interface 54 to the data bus 60.
During a memory access, the logic controller 48 decodes the command signals according to a predetermined protocol to identify the row active state and the column command state for execution by the SDRAM 40. The row active command then transitions the SDRAM 40 to the row active state as shown in FIG. 2. Note that the RAS* signal is active low and the CAS* signal is inactive high in the row active state. As mentioned above, in the row active state, the only address that can be processed by the SDRAM 40 is a row address received on the address bus 52. Thus, in the row active state, there is never a need to process an external column address.
FIGS. 3 and 4 show clock and command signals and their states for write commands and read commands, respectively. Note that, in these commands, the RAS* signal is inactive high and the CAS* signal is active low. The read and write commands differ only in the state of the write-enable signal WF*. The write-enable signal WE* is an active low signal such that, if the write-enable signal WE* is low, the data transfer operation will be a write, as shown in FIG. 3. If the write-enable signal WE* is high, the data transfer operation will be a read, as shown in FIG. 4. In the remaining figures, these combination of command signals corresponding to the read and write commands will be shown as simply a "read" command or a "write" command in the interests of brevity and clarity.
With reference to FIG. 5, a no operation ("NOP") command is the same as the read command shown in FIG. 4 except that CAS* is inactive high rather than active low. The NOP command is used during a burst memory transfer, as explained below. As also mentioned above, an internal address is used for a burst memory transfer while an external column address is used in other memory transfers.
As is conventional to SDRAM operation, the row address is received and stored, and the selected row is activated prior, prior to either a column command or the column address being applied to the address bus 52 (FIG. 1) and the column address strobe signal CAS* going low.
As indicated by the arrow 50 in FIGS. 2-5, the leading edge of each pulse of the clock signal CLK establishes the time at which the states of the signals are determined. The clocking of the logic controller 48 by the clock signal CLK is enabled by the clock-enable signal CKE, which is high for reading and writing. Also, reading and writing from the SDRAM 40 is enabled only when the SDRAM 40 is selected, as indicated by the chip-select signal CS*.
The logic controller 48 decodes the above-described command signals CKE, CLK, CS*, WE*, CAS*, and RAS* to determine whether the SDRAM 40 is to be placed in either the idle, row active, or column command states. The logic controller 48 then controls reading from or writing to the memory array 42 by controlling an I/O interface 54 and input and output data paths 56, 58. The I/O interface 54 is any conventional I/O interface known in the art, and includes typical I/O interface elements, such as sense amplifiers, mask logic, precharge and equilibration circuitry, and input and output gating.
The logic controller 48 causes the multiplexer 79 (FIG. 1) to couple either an external column address from the address latch or buffer 62 or an internal column address from the column address counter/latch 78 based on the nature of the command signals applied to the control logic 48. As explained above, if the row address strobe signal RAS* is inactive high, the SDRAM 40 is in the idle state in which none of the rows of the memory array 40 is yet active. Under these circumstances, the SDRAM 40 cannot be in a burst transfer mode in which the column address counter/latch 78 generates an internal counter address. Thus, the logic controller 48 prevents the multiplexer 79 from coupling an internal column address from the column address counter/latch 78 to the pre-decoder 102 before a row has been activated, and the row address strobe signal RAS* transitions low. However, when the row address strobe signal RAS* has transitioned active low and a row has been activated, then a memory access can either be an access to a column corresponding to a column address or a burst memory access. In the case of a memory access to a column corresponding to a column address, the multiplexer 79 must couple the external address from the address latch or bar for 62 to the pre-decoder 102. In the case of a burst memory access, the multiplexer 79 must couple an internal column address from the column address counter/latch 78 to the pre-decoder 102. In the event the row address strobe signal RAS* is high, the control logic 48 generates an appropriate signal for controlling the multiplexer 79 based on the nature of some of the remaining commands that are applied to the control large 48, as explained below.
The operation of the SDRAM 40 for a burst of four read starting at a first column address followed by a burst of four read starting at a second column address is illustrated FIG. 6. At time t.sub.0 the CLK signal goes high to clock a READ command into the logic controller 48. At the same time, a column address is applied to the address bus 52 of the SDRAM 40. Although not shown in FIG. 6, the column address strobe signal CAS* goes low at t.sub.0 to clock the column address into the column address counter/latch 78 (FIG. 1). The control logic then decodes the READ command to determine that the multiplexer 79 should couple the external address from the address latch or buffer 62 to the pre-decoder 102. The column decoder 84 then causes data to be read from the memory cell in the column corresponding to the column address that intersects the active row corresponding to the last row address.
On the leading-edge of the next clock cycle at t.sub.1, a NOP command is clocking to the SDRAM 40. The column address counter/latch 78 responds to the CLK signal by incrementing, thereby applying a column address to the multiplexer 79 that is one column greater than the previous column address. However, the control logic 48 has not yet determined whether the multiplexer 79 should respond to the internal column address from the column address counter/latch 78 or the external address from the address latch or buffer 62. Therefore, subsequent to t.sub.1, the control logic 48 decodes the NOP command and, on that basis, determines that a burst memory access is in process and that the internal column address should be used. The multiplexer 79 then couples the internal column address to the pre-decoder 102.
In the same manner as described above, the column address counter/latch 78 generates incrementally increasing internal addresses at t.sub.2 and t.sub.3. In each case, the control logic 48 decodes the NOP command and causes the multiplexer 79 to couple the internal column address from the column address counter/latch 78 to the pre-decoder 102.
At the leading-edge of the CLK signal at t.sub.4, a new column command, i.e., a READ from a memory cell at a different column address, is applied to the control logic 48. Shortly after t.sub.4, the control logic 48 has decoded the READ command to determine that the multiplexer 79 should couple the external column address from the address latch or buffer 62 to the pre-decoder 102. Thereafter, the SDRAM 40 responds to the next three NOP commands as a burst of four READ command, as described above.
One problem with the operation of the SDRAM 40 illustrated in FIG. 6 is the time delay needed to determine whether the multiplexer 79 should couple an external column address from the address latch or buffer 62 to the pre-decoder 102 or an internal column address from the column address counter/latch 78 to the pre-decoder 102. As explained above, the control logic 48 does not begin to make this determination until the column command, i.e., a READ, WRITE, or a NOP command is clocked into the control logic 48 at the leading edge of the CLK signal. After the command has been decoded, the control logic 48 must apply a corresponding signal to the multiplexer 79, and the multiplexer 79 must then couple either the internal column address or the external column address to the pre-decoder 102. The amount time required to perform these functions can be considerable. If these functions are not performed quickly enough, the control logic 48 may not control the multiplexer 79 until after the falling edge of the CLK signal when an invalid column address may be present at the address bus 52 or invalid data may be present at the data bus 60, in the case of a write operation. In fact, the primary technique for preventing this problem from occurring is to limit the frequency of the CLK signal so that the multiplexer 79 can couple either the internal column address or the extra column address to the pre-decoder 102 prior to the trailing edge of the CLK signal. However, limiting the frequency of the CLK signal limits the speed at which data can be read from or written to the SDRAM 40.
One reason why conventional SDRAMs 40 cannot operate at optimum speed is the relatively long time required to decide the commands. As shown in FIGS. 2-5, the control logic 48 must decode four command signals (i.e., CS*, RAS*, CAS*, and WE*) to determine the state of the SDRAM 40 and the nature of any column command (i.e., a READ or a WRITE command). The time required for conventional decoder circuits to decode command signals increases markedly with the number of signals that must be decoded. Since the control logic 48 must decode four command signals to determine whether an internal column address or an external column address should be used, decoding the command signals limits the operating speed of conventional SDRAMs. There is therefore a need to be able to increase the rate at which command signals can be decoded to select either an internal or external column address.